Embodiments of the present disclosure relate to a flash memory device, and more particularly to a layout for a flash memory device.
A flash memory device, which is a kind of a memory device, includes a page buffer to program or read a large volume of data for a short period of time. The page buffer performs a programming operation or a read operation of the flash memory device in units of a page.
FIG. 1 is a block diagram illustrating a general flash memory device.
Referring to FIG. 1, a general flash memory device includes a plurality of memory cell arrays 120, and a plurality of page buffers 100. Each of the memory cell arrays 120 includes a plurality of memory cells that store data.
Each memory cell array 120 also includes a plurality of bit lines and a plurality of word lines, and a corresponding page buffer 100 is arranged in a region neighboring the memory cell array 120. A source-pick-up region 115 is arranged between two neighboring page buffers 100 and between two neighboring memory cell arrays 120. That is, a first source-pick-up region 115a may extend along a first side of a first page buffer 100a and a first main memory cell array 120a corresponding to the first page buffer 100a and a second side of a second page buffer 100b and a second main memory cell array 120b corresponding to the second page buffer 100b. 
Each of the page buffers 100 is coupled to a control signal. As shown in FIG. 1, the first page buffer 100a is coupled to a first control signal A, the second page buffer 100b is coupled to a second control signal B, and so on. Each control signal independently controls a page buffer 100 coupled to the control signal, and thus also controls a memory cell array 120 corresponding to the coupled page buffer 100. That is, each of the source-pick-up regions 115 is arranged to separate the memory cell arrays 120, which are controlled based on independent control signals, respectively.
The page buffers 100 are arranged on the basis of the number of bit lines. That is, the page buffers 100 are arranged such that each page buffer 100 coupled to a number of corresponding bit lines can process a predetermined amount of data. For example, as shown in FIG. 1, some page buffers 100 correspond to 2048 bit lines to process 2K bit data, while other page buffers 100 correspond to 576 bit lines to process 72 byte data (i.e., 72 byte*8 bits/byte=576 bit data). Since the number of bit lines (e.g., 2048 BLs) coupled to the first page buffer 100a and the first main memory cell array 120a is different from the number of bit lines (e.g., 576 BLs) coupled to a first low RED buffer 100d and a first RED cell array 120d, the source-pick-up regions 115 are arranged at irregular intervals.
A source transistor TR 130 is arranged between a memory cell array 120 and a corresponding page buffer 100. The source transistor TR 130 includes a plurality of gates. A source terminal located at one side of a gate is coupled to a source line, and a drain terminal located at one side of a gate is coupled to a ground voltage terminal.
As described above, the source-pick-up regions 115 are installed between two neighboring page buffers 100 and each of the page buffers 100 is coupled to a corresponding control signal. Thus, it is difficult to reduce the number of source-pick-up regions 115.
In addition, as described above, the source-pick-up regions 115 are arranged irregularly. Thus, when a source line crosses bit lines, a first length of the source line corresponding to a first page buffer 100a is different from a second length of the source line corresponding to a first RED page buffer 100d. Accordingly, the resistance value corresponding to the first length of the source line is different from the resistance value corresponding to the second length of the source line. That is, resistance values vary at different portions of the source line. Accordingly, a current difference caused by the irregular resistance values may occur.